ASIC Chip-Top Timing Engineer
About The Position
For an exciting well-funded start-up, we are looking for a Chip-Top Timing Engineer.
You will work on complex design, high frequency and low-power budget. Work on full RTL2GDSII flow for leading technology and work with external vendors.
Requirements
Minimum Qualifications
- Experience of 10+ years in backend design
- Strong expertise of full RTL2GDSII including:
- Logic synthesis & equivalence checking
- Constraints definition and writing
- Complicated IP integration
- DFT
- P&R
- Low power design including definition, implementation and verification
- Timing STA
- Focus on chip top timing, eco generation, timing closure
- BS/MS in EE/CE from lead universities
Preferred Qualifications
- Team player
- Highly motivated
- Learning abilities
- Good communication
- Experience in Synopsys/Cadence tools is an advantage
- Low power techniques
- Clock-mesh/ multi source cts
- Hierarchical design flow
- Experience in tape-out procedures
- RTL code reading
