It’s Time
for Retym
Our global team is growing!
Our team is growing quickly, with our headquarters in Silicon Valley, California and our design center in Tel Aviv, Israel.
We’re looking for candidates who thrive in a startup environment to make big contributions to a technology positioned to make a difference in data center infrastructure.
The Retym team is a passionate and cohesive group that is always collaborating as we work towards our mission. If you’re interested in joining us, please apply below.
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Analog Designer
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DFT Engineer
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DFT Tech Lead
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Mixed signal verification engineer
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Senior Verification Engineer
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System Integration Engineer
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Analog Designer
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Analog Layout Designer
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CAD VLSI Engineer
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DFT Engineer
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Senior Back End Engineer
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Verification Engineer
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ASIC Chip-Top Timing Engineer
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Chief Architect
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Field Applications Engineer (FAE)
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Analog Lab Engineer
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Embedded SW Engineer
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Embedded SW Engineer
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Experienced Embedded SW Engineer
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System Engineer
System Engineer
We are looking for an excellent Algo system engineer that experience in the optical communication industry. Responsibilities cover all aspects: technical budgeting, noise, signals, operation
Embedded Software Engineer
For an exciting well-funded start-up, we are looking for an excellent Embedded SW Engineer We are building the product from scratch and looking for an
Algorithm Team Lead
We are looking for an Algo team leader who will run a full activity of advanced algorithm design in the area of coherent optical links.
Layout Design Engineer
Retym is looking for great layout engineers who will develop high end ADC/DAC in an advanced process for optical communication. Minimum Qualifications Experience of 3+
Analog Design Engineer
Retym is looking for the greatest analog engineers who will develop high end ADC/DAC in advanced process for optical communication. Minimum Qualifications Analog-Digital converters FIN
ASIC Architect Lead
Retym is seeking an ASIC Architect Lead for a fast-growing startup. Looking for a strong knowledgeable and experienced person in many aspects of the SoC design
